Computer systems can process communications from sources and provide responses. In a multiprocessor system, one or more network interface cards (NICs) receive communications, and drive an interrupt signal to one or more of the processors to indicate that a communication has been received. The interrupt resolution system in the computer system allows a driver in one of the processors to respond to the interrupt, so that the communication can be processed and a response may be generated. Because the processors may share the processing of interrupts, the processor containing the driver that responds to the interrupt for a communication received from one source may not be the processor that had responded to the interrupt for a prior communication received from that same source.
If the process that ultimately processes the communication requires state information from a prior communication, in the event that the same processor processed the prior communication, the state information may be in the processor's cache. The processing of the communication and the generation of the response in this event is quick and efficient, although in an n-multiprocessor system, such efficient processing may only occur 1/n of the time. The remainder of the time, the prior command was processed by a different process or on a different processor, and so the current state information from the prior communications will not be in the cache of the processor that processes the current communication. If, however, a different one of the processors processed the prior communication, the processor responding to the interrupt and processing the subsequent communication must retrieve the state information from memory or disk, adding time to process the communication and produce a response and reducing the throughput of the system. Such inefficient processing occurs (n−1)/n of the time. As n grows to a larger number, the processing efficiency of the system decreases and the average response time increases.
Other systems have the potential to improve the efficiency and response time of such systems, but can require complex contention management systems for the routing of messages to prevent the simultaneous access of queues or other resources by different processors, and if the other systems are implemented in hardware, can add hardware costs to the multiprocessor system.
What is needed is a system and method that can speed the processing and response to communications in a multiprocessor system without requiring any additional contention management systems and without adding hardware costs to the system.